Conventionally, a memory is coupled to a programmable logic device. Stored in the memory is a configuration bitstream. The bitstream is a representation of a design. When provided to the programmable logic device, the bitstream is stored in configuration memory of the programmable logic device, where it is used to configure programmable logic of the programmable logic device with the design.
Heretofore, a Cyclic Redundancy Codes (“CRC”) checker was used to determine whether a design was transferred from the memory to the programmable logic device without error. Data was transferred serially one bit at a time into to the programmable logic device. For example for a Field Programmable Gate Array (“FPGA”) type of programmable logic device, data was transferred either one bit of data at a time or, to increase throughput, eight bits of data at a time were loaded into the FPGA in parallel. The data was combined into sixteen-bit or thirty-two-bit words, in order to perform a CRC check on the data as it was input to the FPGA. In addition, an FPGA only checks data being read into it, and not whether the data was, correctly stored in memory. If the design instantiated in the programmable logic device was tested to determine if it met performance objectives, this could result is substantial wasted time in debugging to determine that the design was not at fault, rather the problem lay in an improper instantiation in programmable logic of the programmable logic device due to corrupted configuration data. Furthermore, as operating voltages are reduced, the problem of accurate data transfer is exacerbated by a reduction in voltage swing for sensing. For a Complex Programmable Logic Device (“CPLD”) type of programmable logic device, long words, such as 1200-bit words, may conventionally be transferred into the CPLD or transferred between two memories within the CPLD. Having a very large CRC checker, such as one that would check a 1200-bit word, would consume too much space on a CPLD.
Accordingly, it would be desirable and useful to provide means to generate indicia of a problem with a transfer from external or internal memory to configuration memory of a programmable logic device.